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PIC16F87XA
DS39582B-page 112
2003 Microchip Technology Inc.
REGISTER 10-2:
RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
SPEN: Serial Port Enable bit
1
= Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0
= Serial port disabled
bit 6
RX9: 9-bit Receive Enable bit
1
= Selects 9-bit reception
0
= Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1
= Enables single receive
0
= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1
= Enables continuous receive
0
= Disables continuous receive
Synchronous mode:
1
= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0
= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1
= Enables address detection, enables interrupt and load of the receive buffer when RSR<8>
is set
0
= Disables address detection, all bytes are received and ninth bit can be used as parity bit
bit 2
FERR: Framing Error bit
1
= Framing error (can be updated by reading RCREG register and receive next valid byte)
0
= No framing error
bit 1
OERR: Overrun Error bit
1
= Overrun error (can be cleared by clearing bit CREN)
0
= No overrun error
bit 0
RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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